The present invention relates generally to antifuse circuits in integrated circuit devices. More specifically, the present invention relates to methods and apparatus for improving the gate oxide reliability in an antifuse latch circuit.
Antifuse latch circuits may be included in integrated circuit memory devices as part of an address detection circuit. Address detection circuits monitor the row and column addresses of integrated memory cell arrays and enable a redundant row or column within the array when the address of a defective row or column is received. U.S. Pat. No. 5,631,862 to Cutter et al., assigned to the assignee of the present invention and incorporated by reference herein in its entirety, discloses an antifuse bank address detection circuit that includes a bank of self-decoupling antifuse circuits.
For purposes of discussion, an exemplary self-decoupling antifuse latch circuit 10 is shown in FIG. 1. In a program mode, anti fuse latch circuit 10 may be programmed to blow antifuse 28. In a normal operation mode, latch output signal FA may be read to determine whether antifuse 28 has been blown or not. For example, latch output signal FA will be a logic high when antifuse 28 is blown and latch output signal FA will be a logic low when antifuse 28 is not blown.
Antifuse latch circuit 10 includes an output latch 12 and a latch control section 14. Output latch 12 includes three PMOS transistors 16, 18, 20, an inverter 22, and two NMOS transistors 24, 26. PMOS transistors 18, 20 are coupled in parallel with their sources coupled to the drain of PMOS transistor 16 and their drains coupled to the input of inverter 22. The gate of PMOS transistor 18 is coupled to signal RDFUS and the gate of PMOS transistor 20 is coupled to the output of inverter 22. The source of PMOS transistor 16 is coupled to voltage VCC and its gate is coupled to signal MRG. NMOS transistors 24, 26 are coupled in series between the drains of PMOS transistors 18, 20 and ground. The gate of NMOS transistor 24 is coupled to signal RDFUS and the gate of NMOS transistor 26 is coupled to the output of inverter 22. The output of inverter 22 is the latch output signal FA.
Latch control section 14 includes three NMOS transistors 30, 32, 34 and an antifuse 28. Antifuse 28 is coupled between signal CGND and the drain of NMOS drop transistor 30. As used herein, NMOS drop transistor 30 is also known as the xe2x80x9cprotection device.xe2x80x9d The gate of protection device 30 is coupled to voltage VCCP through protection device gate input 36 and its source is coupled to the drain of NMOS transistor 32 at control node 38. The gate of NMOS transistor 32 is coupled to the fuse selection signal FS and its source is coupled to signal BSEL. NMOS transistor 34 is coupled between control node 38 and the input of inverter 22 in the output latch 12. The gate of NMOS transistor 34 is coupled to signal DVC2F, which is typically VCC/2+NMOS threshold voltage, Vt. Signal DVC2F may be used to limit the amount of voltage across the dielectric of unblown antifuses so that the antifuse dielectric does not receive a higher voltage stress across it that than the memory cells in the memory array. For example, if DVC2F=VCC/2+NMOS Vt, then the maximum voltage across an unblown antifuse will be VCC/2, which is what the cell plate of the array is typically set to.
Unblown antifuse 28 forms an open circuit. To blow antifuse 28, thus reducing its resistance and allowing current to flow through it, a voltage of approximately+12 Vdc is temporarily placed across its two terminals. This is accomplished by switching signal BSEL to ground, turning on NMOS transistor 32 by ensuring that fuse selection signal FS is a logic high and switching signal CGND to+12 Vdc. Note that protection device 30 does not need to be turned on to complete the path from anti fuse 28 to ground since the gate of protection device 30 is already coupled to voltage VCCP. VCCP is typically VCC+1.4 volts, or VCC+the threshold voltage, Vt, of the access device+an additional voltage margin to cover process variation. While in this program mode, protection device 30 limits the maximum voltage applied to control node 38 to the voltage VCCP minus the threshold voltage VT of protection device 30. Thus, protection device 30 limits the drain-to-gate voltage of NMOS transistor 32 and the source-to-gate voltage of NMOS transistor 34 to limit the breakdown of the gate oxide and improve reliability. However, when antifuse 28 is blown, a large voltage stress is placed across the gate oxide of protection device 30. This high voltage stress can cause pinholes in the gate oxide of protection device 30 during the burn-in stress portion of the manufacturing process and can reduce the reliability of the antifuse latch circuit 10 during normal operation.
Thus, it would be advantageous to develop a technique and device for reducing or removing the high voltage stress placed across the gate oxide of the protection device 30 once the antifuse 28 has been blown and during normal operation of an antiflise latch circuit.
The present invention relates to methods and apparatus for improving the gate oxide reliability in an antifuse latch circuit.
An antifuse latch circuit with improved gate oxide reliability according to the present invention includes a voltage converter circuit configured to selectively alter the voltage level applied to the gate input of a protection device of the antifuse latch circuit upon receiving a signal. In one embodiment of the invention, the voltage converter is configured to selectively reduce or increase the voltage level of a single signal to be applied to the protection device gate input. In another embodiment of the invention, the voltage converter is configured to selectively switch the protection device gate input between at least two voltage levels.
In yet another embodiment of the invention, the voltage converter circuit comprises a cascade voltage switch logic circuit coupled to the gates of two PMOS transistors. Each PMOS transistor is coupled between the protection device gate input and a separate and distinct voltage level. The cascade voltage logic circuit is configured to selectively switch the protection device gate input between the two voltage levels coupled to the two PMOS transistors.
A method of improving the gate oxide reliability in an antifuse latch circuit according to the present invention comprises applying a signal at a first voltage level to the gate of a protection device of an antifuse latch circuit during the programming of the antifuse and applying the signal at a second voltage level to the gate of the protection device during the reading of the antifuse and during normal operation.